The higher integration density and greater functionality of semiconductor integrated circuit devices have been accompanied by use of a scan path circuit to facilitate a device testing. A scan path circuit is such that when the semiconductor integrated circuit device is tested, the flip-flops in the device are connected serially in the manner of a shift register to construct a scan path, a test signal is input from an external terminal and the result of operation by a combinational circuit is read out via the flip-flops connected in the form of a shift register. When the scan path test is conducted using the scan path circuit, each flip-flop latches scan data from a scan-in terminal (SIN) in response to a scan clock (SC) and outputs the data from a scan-out terminal (SOUT) to the scan-in terminal (SIN) of the next flip-flop or to a scan-out external terminal of the semiconductor integrated circuit. For an example of the structure of a scan path flip-flop circuit, see the specification of Japanese Patent Application Laid-Open No. 2000-2754.
FIG. 4 is a diagram illustrating an example of the structure of a conventional flip-flop circuit having a reset function.
As shown in FIG. 4, the flip-flop circuit has a master/slave-type flip-flop structure equipped with a reset/set function. A first NAND gate 101 and a second NAND gate 102 compose a master latch, and a third NAND gate 103 and a fourth NAND gate 104 compose a slave latch.
A first inverter 111 has an input terminal connected to a data terminal DATA, and a first CMOS transfer gate 121, which is turned on and off by a clock signal, is provided between the output terminal of the first inverter 111 and a second input terminal of the first NAND gate 101. A set terminal SETB is connected to the input terminal of a buffer (non-inverting buffer) 110 the output terminal of which is connected to first input terminals of the first and fourth NAND gates 101, 104, respectively.
The output terminal of the first NAND gate 101 is connected to the second input terminal of the second NAND gate 102, the first input terminal of the second NAND gate 102 is connected to a reset terminal (inverting) RESETB, and second and third CMOS transfer gates 122 and 123, respectively, are serially connected between the output terminal of the second NAND gate 102 and the second input terminal of the first NAND gate 101. A first scan clock SC1 and a clock CLK are input to control terminals of the second and third CMOS transfer gates 122 and 123, respectively.
A scan-in input terminal SIN is connected to the input terminal of a second inverter 112, and a fourth CMOS transfer gate 124, which has a control terminal to which the first scan clock SC1 is input, is connected between the output terminal of the second inverter 112 and the connection node of the second and third CMOS transfer gates 122 and 123, respectively.
Fifth and sixth CMOS transfer gates 125 and 126 are serially connected between the output terminal of the first NAND gate 101 and the first input terminal of the third NAND gate 103. The fifth and sixth CMOS transfer gates 125 and 126 have control terminals to which a second scan clock SC2 and the clock CLK, respectively, are input. The third NAND gate 103 has a second input terminal connected to the reset terminal RESTB.
The third NAND gate 103 has its output end connected to an output terminal Q via a third inverter 113, and the third NAND gate 103 has its output end connected to the second input terminal of the fourth NAND gate 104. As mentioned above, the first input terminal of the fourth NAND gate 104 is connected to a set terminal SETB.
A seventh CMOS transfer gate 127, which is turned on and off by the clock signal CLK, is connected between the output terminal of the fourth NAND gate 104 and the input terminal of the third NAND gate 103. An eighth CMOS transfer gate 128, which is turned on and off by the second scan clock SC2, is connected between the output terminal of the fourth NAND gate 104 and the node of the fifth and sixth CMOS transfer gates 125 and 126.
An inverted clock CLKB and the uninverted clock CLK are supplied to the gates of a P-channel MOS transistor and N-channel MOS transistor of the first and seventh CMOS transfer gates 121 and 127, and the uninverted clock CLK and inverted clock CLKB are supplied to the gates of a P-channel MOS transistor and N-channel MOS transistor of the third and sixth CMOS transfer gates 123 and 126. It should be noted that inverted clock CLKB is obtained as a result of inverting the clock CLK by an inverter INV1.
The uninverted scan clock SC1 and an inverted scan clock SC1B are supplied to the gates of a P-channel MOS transistor and N-channel MOS transistor of the second CMOS transfer gate 122. It should be noted that the inverted scan clock SC1B is obtained as a result of inverting the uninverted scan clock CLK by an inverter INV2.
The inverted scan clock SC1B and the uninverted scan clock SC1 are supplied to the gates of a P-channel MOS transistor and N-channel MOS transistor of the fourth CMOS transfer gate 124.
An inverted scan clock SC2B and the uninverted scan clock SC2 are supplied to the gates of a P-channel MOS transistor and N-channel MOS transistor of the fifth CMOS transfer gate 125. The inverted scan clock SC2B is obtained as a result of inverting the uninverted scan clock SC2 by an inverter INV3. It should be noted that the scan clocks SC1 and SC2 are assumed below to be two-phase signals that do not overlap.
The uninverted scan clock SC2 and inverted scan clock SC2B are supplied to the gates of a P-channel MOS transistor and N-channel MOS transistor of the eighth CMOS transfer gate 128.
During ordinary operation, the first scan clock SC1 is fixed at the low level, the second scan clock SC2 is fixed at the high level and only the clock CLK is supplied.
As a result of the scan clocks SC1 and SC2 being fixed at low and high levels, respectively, the second CMOS transfer gate 122 is placed in the ON state, the fourth CMOS transfer gate 124 in the OFF state, the fifth CMOS transfer gate 125 in the ON state and the eighth CMOS transfer gate 128 in the OFF state, and the input path from the scan-in terminal SIN to the master latch and the connection path between the slave latch and the scan-out terminal SOUT are cut.
Normal operation when both the set and reset signals are inactive will now be described.
FIG. 5 is a timing chart useful in describing operation of the circuit of FIG. 4 when the circuit is functioning normally. When the set signal (inverted) SETB is inactive (at the high level), the first and fourth NAND gates 101 and 104 take on logic equivalent to that of inverter elements. When the reset signal RESETB is inactive (at the high level), the second and third NAND gates 102 and 103 take on logic equivalent to that of inverter elements.
When the clock CLK is at the high level (CLKB is at the low level), the first and seventh CMOS transfer gates 121 and 127 turn on and the third and sixth CMOS transfer gates 123 and 126 turn off.
Conversely, when the clock CLK is at the low level (CLKB is at the high level), the third and sixth CMOS transfer gates 123, 126 turn on and the first and seventh CMOS transfer gates 121, 127 turn off.
When the clock signal CLK is at the high level, which is at time T1 in FIG. 5, a signal that is the result of inverting the signal level of the data (DATA) terminal enters the second input terminal of the first NAND gate 101. The latter inverts this value, which is the result of inverting the signal logic of the DATA terminal, and inputs the inverted value to the second input terminal of the second NAND gate 102.
When the clock signal CLK falls to the low level, which occurs at time T2, the sixth CMOS transfer gate 126 turns on, the output of the first NAND gate 101 is transmitted to the first input terminal of the third NAND gate 103 via the ON fifth and sixth CMOS transfer gates 125, 126, the third NAND gate 103 supplies the input terminal of the third inverter 113 and the second input terminal of the fourth NAND gate 104 with a signal obtained by inverting the logic value at the first input terminal of the third NAND gate 103, and the output of the third NAND gate 103 is inverted by the inverter 113 and output from the output terminal Q. Further, the fourth NAND gate 104 (the first input terminal of which is connected to the SETB terminal and is at the high level) outputs a signal, which is the result of inverting the logic value at the second input terminal of the fourth NAND gate 104, to the scan-out terminal SOUT. At this time the first CMOS transfer gate 121 turns off, the connection between the second input terminal of the first NAND gate 101 and the data terminal is severed, the third CMOS transfer gate 123 turns on and the master latch latches the input data.
When the clock signal CLK rises to the high level, which occurs at time T3, the sixth CMOS transfer gate 126 turns off and the master latch and slave latch are cut off from each other. In the slave latch, the seventh CMOS transfer gate 127 turns on so that the output of the fourth NAND gate 104 is connected to the input of the third NAND gate 103, whereby the slave latch latches the data. It should be noted that if the second scan path clock SC2 and the inverted signal SC2B thereof connected to the gates of the P-channel MOS transistors and N-channel MOS transistors of the fifth and eighth CMOS transfer gates 125, 128 are made the opposite of the what is shown in FIG. 4, the second scan path clock SC2 will be fixed at the low level.
A shift operation performed at the time of a scan path test will now be described. At the time of a scan path test, the clock CLK is fixed at the low level. The first and seventh CMOS transfer gates 121, 127 turn off and the third and sixth CMOS transfer gates 123, 126 turn on.
FIG. 6 is a timing chart useful in describing operation of the circuit of FIG. 4 at the time of a scan shift.
When the first scan clock SC1 is at the high level (the second scan clock SC2 is at the low level), which is at time T1 in FIG. 6, a signal that is the result of inverting the signal at the scan-in terminal SIN enters the second input terminal of the first NAND gate 101 via the fourth CMOS transfer gate 124 and third CMOS transfer gate 123. The output of the first NAND gate 101 (the signal logic at the SIN terminal) enters the second input terminal of the second NAND gate 102. When the first scan clock SC1 is at the high level (SC2 is at the low level), the second CMOS transfer gate 122 is off.
When the first scan clock SC1 falls to the low level (SC2 is at the low level), which occurs at time T2, the fourth CMOS transfer gate 124 turns off, the electrical connection between the scan-in terminal SIN and master latch is severed, the second CMOS transfer gate 122 turns on, the equivalent of a two-inverter flip-flop, which comprises the first and second NAND gates 101, 102 of the master latch, is formed, and the signal at the scan-in terminal SIN is latched.
When the scan clock SC2 rises to the high level (SC1 is at the low level), which occurs at time T3, the fifth CMOS transfer gate 125 turns on, the output of the first NAND gate 101 (i.e., the signal logic at the SIN terminal) is input to the second input terminal of the third NAND gate 103 via the fifth CMOS transfer gate 125 and sixth CMOS transfer gate 126, the output of the third NAND gate 103 (the logic value obtained by inverting the signal at the SIN terminal) enters the second input terminal of the fourth NAND gate 104, and the output of the fourth NAND gate 104 (the signal which is the inverse of the output of the third NAND gate 103) is delivered from the scan-out terminal SOUT. That is, a signal whose logic is the same as that of the output terminal Q is output also as the scan-out terminal SOUT. In FIG. 4, a terminal (QB) for providing the inverse of the signal at the output terminal Q is not shown. However, the inverted output signal is obtained from a terminal connected to the node between the output terminal of the third NAND gate 103 and the third inverter 113 (or it may be obtained via a non-inverting buffer).
When the scan clock SC2 reverts to the low level at time T4, the fifth CMOS transfer gate 125 turns off and the slave latch is severed from the master latch. In the slave latch, the eighth CMOS transfer gate 128 turns on, the equivalent of a two-inverter flip-flop, which comprises the third and fourth NAND gates 103, 104, is formed, and the data is latched. It should be noted that if the second scan path clock SC2 and the inverted signal SC2B thereof connected to the gates of the P-channel MOS transistors and N-channel MOS transistors of the fifth and eighth CMOS transfer gates 125, 128 are made the opposite of the what is shown in FIG. 4, the second scan path clock SC2 will become a signal that is the inverse of the signal shown in FIG. 6 (i.e., the high/low levels of the signal will be reversed).
Operation in a case where the set terminal SETB is active (at the low level) at the time of normal operation will now be described. In this case, the reset terminal RESETB is inactive (at the high level).
When the set terminal SETB assumes the low level, the output of the first NAND gate 101, whose first input terminal has been placed at the low level, and the output of the fourth NAND gate 104 both assume the high level. When the clock CLK is at the low level, the sixth CMOS transfer gate 126 turns on, the output signal of the first NAND gate 101 is transmitted to the first input terminal of the third NAND gate 103, and the third NAND gate 103 inverts and outputs the signal level (high in this case) of its first input terminal (the second input terminal of the third NAND gate 103 is connected to the RESETB terminal and is at the high level). As a result, a high level is output from the output terminal Q. At this time the output terminal of the fourth NAND gate 104 delivers a high-level signal also to the scan-out terminal SOUT asynchronously with respect to the clock.
When the clock CLK attains the high level, the seventh CMOS transfer gate 127 turns on, the sixth CMOS transfer gate 126 turns off (the slave latch is disconnected from the master latch) and the high level from the output terminal of the fourth NAND gate 104 enters the first input terminal of the third NAND gate 103. As a result, the state is maintained at the high level of the output terminal Q.
Next, operation in a case where the reset terminal RESETB is active (at the low level) at the time of normal operation will be described. In this case, the set terminal SETB is inactive (at the high level).
When the reset terminal RESETB assumes the low level, the outputs of the second and third NAND gates 102, 103 attain the high level, the output of the third NAND gate 103 is inverted and output by the third inverter 113, and the output terminal Q delivers the low level asynchronously. At this time, the first and second input terminals of the fourth NAND gate 104 attain the high level and the output terminal of the fourth NAND gate 104 delivers the low level to the scan-out terminal SOUT.
In response to the low level of the clock CLK, the third CMOS transfer gate 123 turns on, the high level is supplied to the second input terminal of the first NAND gate 101 and the first NAND gate 101 outputs the low level because its first input terminal is at the high level (SETB). This low-level signal is output to the first input terminal of the third NAND gate 103.
In response to the high level of the clock CLK, the seventh CMOS transfer gate 127 turns on, the sixth CMOS transfer gate 126 turns off and a low level is supplied to the first input terminal of the third NAND gate 103 from the output terminal of the fourth NAND gate 104.
Operation in a case where the set terminal SETB is active (at the low level) at the time of the scan path test will now be described. In this case, the reset terminal RESETB is inactive (at the high level). The clock CLK is placed at the low level, the first and seventh CMOS transfer gates 121, 127 turn off and the third and sixth CMOS transfer gates 123, 126 turn on.
At the moment the set terminal SETB assumes the low level, the fourth NAND gate 104 immediately outputs the high level and the high level is output to the scan-out terminal SOUT asynchronously.
The output terminal of the first NAND gate 101 whose first input terminal is connected to the set terminal SETB attains the high level, the fifth CMOS transfer gate 125 is turned on owing to the high level of the second scan clock SC2, the output signal of the first NAND gate 101 is transmitted to the first input terminal of the third NAND gate 103, the third NAND gate 103 inverts and outputs the signal level at its first input terminal, and the output of the third NAND gate 103 is inverted and output by the third inverter 113, whereby a high level is output.
When the scan clock SC2 reverts to the low level, the eighth CMOS transfer gate 128 turns on, the fifth CMOS transfer gate 125 turns off and the high level is input to the first input terminal of the third NAND gate 103. As a result, the high level at the scan-out terminal SOUT is latched.
Next, operation in a case where the reset terminal RESETB is active (at the low level) at the time of the scan test will be described. In this case, the set terminal SETB is inactive (at the high level).
When the reset terminal RESETB assumes the low level, the outputs of the second and third NAND gates 102, 103 attain the high level, the logic at the output of the third NAND gate 103 is inverted and output by the third inverter 113, the low level is output at the output terminal Q and the output terminal of the fourth NAND gate 104 delivers the low level also to the scan-out terminal SOUT. In other words, the scan-out terminal SOUT outputs the low level asynchronously irrespective of the scan clock.
Furthermore, in response to the low level of the scan clock SC1, the second CMOS transfer gate 122 turns on, the high level is supplied to the second input terminal of the first NAND gate 101, and the first NAND gate 101 outputs the low level because its first input terminal is at the high level (SETB). This low-level signal is output to the first input terminal of the third NAND gate 103.
In response to the low level of the scan clock SC2, the eighth CMOS transfer gate 128 turns on, the fifth CMOS transfer gate 125 turns off and the low level output of the fourth NAND gate 104 is supplied to the first input terminal of the third NAND gate 103, whereby the slave latch latches the output signal.
In order for the operation of the shift register constructing the scan path to be carried out correctly, it must be so arranged that the values of the scan path flip-flops will not be changed by the shift operation.
More specifically, when the input from the reset terminal RESETB for inputting the signal from the logic circuit that generates the reset signal is set from the high level to the low level or falls to the low level owing to noise or the like at the time of the scan path test, an erroneous signal will propagate through the shift register if the output SOUT of the scan path flip-flop is forcibly reset to the low level and this output is input to the scan-in terminal of the scan path flip-flop of the next stage. This holds true for the set signal as well.
In order to so arrange it that an active signal will not be supplied to the set and reset terminals of the scan path flip-flop owing to operation of the logic circuit, which supplies the set and reset signals, at the time of the scan path test, it is necessary to supply a pattern that will control the set/reset signal generating logic circuit in such a manner that this circuit will not operate at the time of test. Furthermore, it is necessary to perform the test with a pattern and timing margin that will not produce glitch noise or the like in the reset and set signals. As a consequence, automatic pattern design and testing is difficult.
A scan path flip-flop not having a set and/or reset function can have its output provided with a holding circuit for holding data, and circuit design is possible without taking a change in the output logic of the flip-flop into account at the time of the shift operation. Such as arrangement is disclosed in, e.g., the specification of Japanese Patent Application Laid-Open No. 62-239071. However, even if the output terminal of a scan path flip-flop equipped with a set and/or reset function is provided with a holding circuit, any change in state caused by setting or resetting of the flip-flop at the time of a shift operation during a scan path test will be transmitted to the next flip-flop stage.
Further, the specification of Japanese Patent Application Laid-Open No. 7-306244, for example, discloses a flip-flop in which a logic circuit is connected to set and reset terminals. Specifically, this specification discloses a flip-flop in which the outputs of a first AND element and second AND element are connected to the set and reset terminals, respectively, one input terminal of the second AND element is connected to the output of an inverting element, one input of the first AND element and the other input of the second AND element are made a load timing (LT) input, and the other input of the first AND element and input of the inverting element are made load data (LD). It is so arranged that an asynchronous clock is supplied to the flip-flop directly at the time of ordinary operation and that the scan path of the flip-flop is constructed when a test is performed. At the time of ordinary operation, a circuit-design limitation to the effect that a synchronous clock must not be used is eliminated, and an asynchronous clock is supplied to the flip-flop directly without the intermediary a selector. This solves the problem that high-speed operation, in which a deviation in clock skew at the time of ordinary operation becomes an obstacle, is difficult to achieve in a case where the asynchronous clock for ordinary operation or the synchronous clock for the test operation is being supplied as the flip-flop clock via the selector. However, even this circuit arrangement does not make it possible to avoid erroneous setting of set and reset when a shift operation is performed during a scan path test.